There exist integrated configurable circuits to encode data according to any one of a plurality of coding schemes and/or to generate cycle redundancy codes. Typically, the code scheme comprises block, convolutional and turbo codes.
Ideally such a circuit should be very flexible, that is, able to be configured to execute many different coding schemes and/or to generate many different cyclic redundancy codes. This circuit should also excel in the efficient execution (power, chip area, flexibility) of these schemes. However, flexibility and execution efficiency are inversely related. For example, a more flexible circuit results in slower execution speed. In contrast, a faster circuit is less flexible. Attempts to build circuits which are pretty flexible while remaining fast have been disclosed. For example, U.S. Pat. No. 6,807,155 to Subramanian discloses ranking functions which are common to different telecommunication processing standards according to their computational intensity. The design of the telecommunication processing is based on the function ranking to speed up the execution while remaining flexible.